A Timing - Driven Soft - Macro Resynthesis Method in Interactionwith

In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip oorplanning for area and timing improvements. We develop a timing-driven design ow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-eecient designs while satisfying the timing constraints. Experiments on a number of industrial designs have demonstrated that by eeectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.